A frequency synthesizer is an electronic device for providing an output frequency based on an input reference frequency. For example, a fractional-N synthesizer is a frequency synthesizer widely used in many modern devices, including radio receivers, mobile telephones, global positioning systems, etc. The fractional-N synthesizer has advantages over other types of frequency synthesizers, including reduced generation of phase noise and spur levels.
FIG. 1 illustrates a conventional fractional-N synthesizer 100. The fractional-N synthesizer 100 is configured to generate an output signal Sout with a frequency fout based on an input signal Sref with a reference frequency fref generated by a clock source, such as a crystal oscillator (not shown). The output frequency fout is approximately equal to the reference frequency fref multiplied by an adjustable factor D, where the factor D can be an integer or non-integer.
Referring to FIG. 1, the fractional-N synthesizer 100 includes a phase/frequency detector (PFD) 102, a charge pump 104 coupled to the PFD 102, a voltage controlled oscillator (VCO) 106 coupled to the charge pump 104, a loop filter 108 coupled to a node between the charge pump 104 and the VCO 106, and a frequency divider 110 coupled between the VCO 106 and the PFD 102. The frequency divider 110 is configured to provide the adjustable factor D such that the output frequency fout may be adjusted by adjusting the factor D.
The charge pump 104 includes first and second current sources 104-1 and 104-2 coupled in series via a node N. The current sources 104-1 and 104-2 may be metal-oxide-semiconductor (MOS) transistors and provide first and second currents Iup and Idown, respectively. For example, the current source 104-1 may be a PMOS transistor, and the current source 104-2 may be an NMOS transistor.
The charge pump 104 and the loop filter 108 produce a voltage VN at the node N, that is applied to the VCO 106. The VCO 106 generates the output signal Sout with the frequency fout that varies with the voltage VN. For example, the frequency fout of the output signal Sout may increase as the voltage VN increases. The frequency divider 110 receives the output signal Sout with the frequency fout and generates a feedback signal Sfb with a frequency ffb approximately equal to 1/D of the frequency fout.
The PFD 102 receives the input signal Sref with the reference frequency fref and the feedback signal Sfb with the frequency ffb, and compares a phase or frequency difference between the input signal Sref and the feedback signal Sfb. The PFD 102 further provides first and second switch signals Sup and Sdown to turn on the first and second current sources 104-1 and 104-2, respectively, based on the phase or frequency difference.
For example, if the PFD 102 determines that the frequency ffb of the feedback signal Sfb is smaller than the reference frequency fref of the input signal Sref, the PFD 102 may send the first switch signal Sup to turn on the first current source 104-1. Accordingly, the current Iup provided by the first current source 104-1 charges the loop filter 108, such that the voltage VN applied to the VCO 106 increases. As a result, the frequency fout of the output signal Sout and, hence, the frequency ffb of the feedback signal Sfb also increase.
Also, for example, if the PFD 102 determines that the frequency ffb is larger than the reference frequency fref, the PFD 102 may send the second switch signal Sdown to turn on the second current source 104-2. Accordingly, the current Idown provided by the second current source 104-2 discharges the loop filter 108, such that the voltage VN applied to the VCO 106 decreases. As a result, the frequency fout of the output signal Sout and, hence, the frequency ffb of the feedback signal Sfb also decrease.
These operations are repeated until the PFD 102 determines that the frequency ffb is approximately equal to the reference frequency fref, which corresponds to a state in which the fractional-N synthesizer 100 is in a locked condition. In the locked condition, the fractional-N synthesizer 100 generates the output signal Sout with the frequency fout approximately equal to the reference frequency fref multiplied by the factor D.
In the locked condition, the PFD 102 sends the switch signals Sup and Sdown to turn on the first and second current sources 104-1 and 104-2 for substantially the same short period of time. Ideally, the current Iup provided by the current source 104-1 is substantially the same as the current Idown provided by the current source 104-2. Therefore the charge pump 104 outputs a zero net current when the fractional-N synthesizer 100 is in the locked condition. However, in reality, there may be a charge pump current mismatch such that the current Iup may be not equal to the current Idown. For example, a difference between drain-source voltages applied to the PMOS transistor and the NMOS transistor, respectively operating as the first and second current sources 104-1 and 104-2, may cause the current mismatch.
As a result, the charge pump 104 may output a net current I0, which is the difference between the first and second currents Iup and Idown, when the fractional-N synthesizer 100 is in the locked condition. The net current I0 may flow into or out of the charge pump 104 via the node N depending on whether the current Iup is smaller or larger than the current Idown. The current mismatch may degrade performance of the fractional-N synthesizer 100.